Modern PDA products and combination cell phone/PDA products, referred from this point forward as portable devices, require substantial amounts of memory. While many portable devices are assembled with multiple discrete components, cost and performance pressures point to single-chip system on chip (SoC) implementations as the optimal solution. Such applications, like most other semiconductor devices, tend to be built on high-volume standard processes, such as standard logic processes to keep fabrication costs under control.
For consumers, battery life of portable devices is a primary concern, hence power consumption of the portable device should be kept as low as possible. Moreover, these portable devices preferably operate on very low power in standby mode. While many functions can be shut down in standby mode, memory cannot be lost. Thus the optimal approach is to use some form of non-volatile memory. Unfortunately, Flash memory is not presently compatible with standard logic processes, and ferro-electric memories are not presently a high-volume standard process.
Therefore, the most promising and practical memory for portable devices is DRAM, and more specifically embedded DRAM (eDRAM) for SoC implementations. There is already a clear trend for embedding DRAM compatible with standard logic processes into SoC products. The advantages are demonstrated in products that can be made smaller, consume less power while operating faster than their discrete component system counterparts. Although SRAM memory can be used, SRAM memory arrays consume more silicon area than a DRAM memory array of the same density.
As known to those of skill in the art, DRAM requires periodic refreshing of its data, which contributes to power consumption. Hence portable devices having eDRAM can benefit if the period between refresh operations is extended as much as possible. In the standby mode of the portable device, battery life can be extended by minimizing refresh power consumption.
Unfortunately, the reliability of an embedded DRAM to operate properly generally requires some minimum capacitance value for memory cell charge storage. Reliability in the memory context commonly refers to the ability of a memory cell to retain the logic level written to it. The logic state of a DRAM memory cell can change due to leakage of its stored charge over time, or due to random alpha particle hits, either of which can result in system errors. Furthermore, different DRAM cells can leak charge at different rates. The refresh interval is thus set to accommodate the fastest leaking DRAM cell, and cannot be overly extended to save power.
Data reliability is a problem that has been addressed in the telecommunications and mass storage fields, where wireless transmissions are susceptible to signal degradation and mass storage media such as compact discs and computer hard disk drives routinely encounter read errors. The detection and correction of “bad bits” of data to improve reliablity is achieved through Error Correction Coding (ECC) techniques. Many ECC techniques and coding schemes are well known in the art, and therefore do not require further description.
Accordingly, ECC has been used in memory systems, and over the years papers have appeared describing a variety of memory chips including the function within the chip. Most are based on “Hamming” codes, Modified Hamming, or Reed-Solomon codes. The additional silicon area consumption and impact upon performance due to added overhead limit such chips to very specific applications, and hence have not seen widespread commercial use. These issues become more serious, when seeking to apply ECC to a compiled embedded memory where the size and word length of the memory are, by definition, variable. Hence an ECC scheme tailored for one particular embedded memory configuration may not apply to an embedded memory having a different configuration. Those of skill in the art should understand that a compiled embedded memory is produced with the aid of computer software tools through which designers can specify memory bank sizes, the number of memory banks, and other parameters, to suit a specific application.
A published ECC scheme for standard memory devices that showed some promise was a two-dimensional linear parity encoding scheme. FIG. 1 illustrates the principle of two-dimensional linear parity encoding with a 16 by 16 memory cell array. To simplify the illustration, wordlines, bitlines or peripheral circuits such as bitlines and column access devices are not shown. Memory array 20 is composed of memory cells arranged in rows and columns, where each square 22 represents a memory cell. This configuration is well known in the industry. One additional row and column of memory cells are added to memory array 20, where the additional row is a parity row 24 and the additional column is a parity column 26. Hence, if a rectangular array of memory cells can be checked for parity in orthogonal directions, the intersection of the failing lines defines a bad bit. In the example shown in FIG. 1, the row of a bad bit 28 can be identified by checking the parity of its associated row of memory cells against the parity column bit 30 in the same row. Correspondingly, the column of bad bit 28 can be identified by checking the parity of its associated column against the parity row bit 32 in the same column. Therefore bad bit 28 can be identified for correction of its data. Moreover, any two bad bits in the array can be detected and corrected so long as no two bad bits appear on the same line.
Known methods for implementing the two-dimensional linear parity encoding scheme for DRAM were found to be clumsy, adding excessive amounts of wide bussing as well as the ECC circuitry itself. Although the increase in chip size due to the added parity rows and columns is unavoidable, the increase due to the additional wide bussing and ECC circuitry further reduced the cost effectiveness and advantages of adding the error correction capability.
Another problem inherent to most memory ECC schemes is their inability to correct, or purge, the memory cell identified with the faulty data. If the data is corrected only at read out, then the memory array will accumulate bad bits over time. Although some schemes then purge the memory cell with corrected data, they can do so only during a read access. Hence bad bits can accumulate in between read access operations, especially if the interval between read access operations is long. Naturally, error correcting at read out also impacts device performance due the additional logic overhead of the ECC circuits.
It is, therefore, desirable to provide a memory ECC architecture that occupies minimal silicon chip area, and performs error detection and purging with minimum impact upon device performance.